Semiconductor chips are fabricated on suitable flat substrate wafers, such as GaAs, diamond coated substrates, silicon carbide, silicon wafers, etc. After making the active devices, a series of steps are performed to connect the various devices with highly conducting wiring structures, so they can have communication with each other to perform logic or memory storage operations. These wiring structures or interconnect structures are essentially a skeletal network of conducting materials, typically metals, in a matrix of dielectric materials. In high performance devices and to improve device density and yield, it is desirable to minimize topographic features within the interconnect layers for any given device and across the entire substrate. One common method of forming these high-performance interconnect layers is the damascene process.
Multiple types of damascene structures are known, however single and dual damascene processes are the most common. In single damascene, each metal or via layer is fabricated in a series of operations, while in dual damascene, a metal level and a via level are fabricated in a similar operation. Of these two, the dual damascene technique is often preferred because of lower cost and higher device performance.
In the dual damascene process, a suitable substrate with or without devices is coated with a suitable resist layer. The resist layer is imaged to define desirable patterns by lithographic methods on the substrate. Cavities are etched on the patterned substrates typically by reactive ion etching (RIE) methods. The patterned substrate is then coated with a suitable barrier/seed layer prior to overfilling the cavities with a suitable metal, typically copper, by electro-deposition from super-filling plating bath chemistry. After subjecting the coated substrate to a thermal treatment process, the coated conductive layer on the substrate is planarized to remove any unwanted conductive layers. During the planarization step, portions of the underlying dielectric layer may also be removed.
The damascene process is repeated to form the many layers of interconnects. As a result of the discontinuity in the properties (difference in mechanical properties, polishing rates, etc.) of the interconnect metal and the surrounding insulator material, and their respective interactions with the polishing pad, polishing slurry, and other process parameters, erosion forms in areas of high metal pattern density features and dishing forms in large metal structures. The higher the metal pattern density, the greater the erosion, and similarly, the larger the size (e.g., area) of the metal structure, the greater the dishing defect. These deleterious defects can be problematic for manufacturing complex structures, causing shorting defects in subsequent levels, and reducing device yield.
Similar results are observed in cross section topographic profiles of polished through silicon via (TSV) structures. The centers of the vias are often typically lower than the surface of the insulators, due to the dishing effects described.
One of the consequences of substrate surface dishing is poor flatness of the surface of the substrate and its interconnects. This can cause much higher pressures to be needed for bonding devices, dies, wafers, substrates, or the like, using so called hybrid bonding techniques. For example, dies and/or wafers may be bonded in a stacked arrangement using various bonding techniques, including direct bonding, non-adhesive techniques known as ZiBond® or a hybrid bonding technique, also known as DBI®, both available from Invensas Bonding Technologies, Inc., a Xperi company (see for example, U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety). These bonding techniques, and other similar techniques, require extremely flat bonding surfaces for the most reliable and the best performing bonds.
Attempts to reduce the impact of these defects have included the incorporation of dummy dielectric or metal features in the layout of the design of device interconnects. This approach has been helpful, but it has also increased mask design complexity and the associated loss of freedom of structure placement on the modified pads.